As is known, for numerous applications of microelectronics, there has risen the need to integrate in a single semiconductor chip low-voltage devices and power devices (which operate with voltages that range from approximately 15 V up to beyond 1000 V). In particular, it has become increasingly frequent to make low-voltage devices by CMOS technology in a first portion of the chip and power devices, compatible with the CMOS technology, in a second portion of the same chip. The active areas that house the various devices, both low-voltage devices and power devices, are insulated from one another by shallow-trench-insulation (STI) technique, which enables an extremely high degree of integration to be achieved, with extremely small overall dimensions, and for this reason is typically used in CMOS technology. In practice, the substrate of a semiconductor wafer is selectively etched through a hard mask, for example a multilayer mask of silicon oxide and silicon nitride, and trenches are formed that delimit and separate active areas for low-voltage devices and active areas for power devices. The trenches are oxidized and completely filled with deposited dielectric, normally silicon oxide. The wafer is then planarized, and the hard mask is thus removed. The active areas are hence separated from one another by insulating structures with practically vertical walls, which extend for a stretch in the substrate.
Manufacture of power devices with CMOS technology, in particular in active areas defined by STI, however, may present limits when the scale of integration is pushed beyond a certain threshold. These limits have become manifest with 0.25-μm technology and even more evident with 0.18-μm technology. As already mentioned, the walls of the STI structures are almost vertical (normally inclined at 80°-90°), to minimize the extension of the areas of transition between thin oxide (gate oxide) and thick oxide, and thus reduce the overall dimensions. The corresponding interface in the silicon hence presents equally marked angles, as is shown in FIG. 1, where/designates a substrate of semiconductor material, in which an STI structure 2 has been made. The substrate/and the STI structure 2 are overlaid by a gate-oxide layer 3 and by a gate region 4 made of polycrystalline silicon. The angle α formed between the faces of the substrate/respectively contiguous to the STI structure 2 and to the gate-oxide layer 3 is 180°−β, where β is the slope of the walls of the STI structure 2. The angle α is hence approximately 90°-100° and may cause a significant concentration of the electrical-field lines, in particular in the proximity of the region where the channel of the power device is formed. The concentration of the electrical-field lines may have an adverse effect both on the active-state resistance (RON, which may be high and unstable on account of injection of hot carriers) and on the breakdown voltage (BV) of the power components. In effect, there may arise problems of reliability and performance that render incompatible the conventional use of STI to obtain power components integrated with low-voltage CMOS devices.